The present invention relates to a method for fabricating a thin film transistor, and more particularly to a method for fabricating a thin film transistor capable of increasing an ON/OFF current ratio and decreasing a consumption of electric power.
Generally, thin film transistors are used in static random access memory (SRAM) devices of one mega-bit grade or greater, in place of load resistors. In liquid crystal displays (LCDs), such thin film transistors are widely used as switching devices for switching image data signals in pixel regions.
FIG. 1 is a circuit diagram of a high resistance-loaded SRAM. As shown in FIG. 1, the high resistance-loaded SRAM includes a pair of NMOS transistors Q.sub.1 and Q.sub.2 which are of flip-flops including crossing inverters having resistors R.sub.1 and R.sub.2 as their loads, respectively, to constitute a unit cell.
The unit cell is connected to data lines B/L and B/L by sources and drains of respective NMOS transistors Q.sub.3 and Q.sub.4. The gates of NMOS transistors Q.sub.3 and Q.sub.4 are connected to word lines W/L.sub.1 and W/L.sub.2, respectively.
When the word lines W/L.sub.1 and W/L.sub.2 are at a high level in the SRAM, the NMOS transistors Q.sub.3 and Q.sub.4 are turned on, so that the unit cell is electrically connected to both the data lines B/L and B/L. For recording data of "1" under the above condition, a signal of 5 V corresponding to the data "1" is applied to the data line B/L. On the other hand, a signal of "0" (zero volt) is applied to the data line B/L. As a result, the transistor Q.sub.1 is turned off while the transistor Q.sub.2 is turn on. Accordingly, the node N.sub.1 charges up through the transistor Q.sub.3 and keeps this state.
On the contrary, when data of "0" is to be recorded, a signal of "0" is applied to the data line B/L while a signal of "1" is applied to the data line B/L. By these signals, the transistor Q.sub.1 is turned on whereas the transistor Q.sub.2 is turned off. As a result, the node N.sub.2 charges up through the transistor Q.sub.4 and keeps this state.
In the SRAM wherein data are stored by the above-mentioned operations, a standby current I.sub.SB generated when data of "1" is recorded can be expressed by the following equation (1) with respect to a current I.sub.R flowing the resistor R.sub.2 and a leakage current I.sub.leak from the transistor Q.sub.1. EQU I.sub.SB =I.sub.R +I.sub.leak ( 1)
In the equation (1), the leakage current I.sub.leak from the transistor Q.sub.1 should not be more than 10 fA while the current I.sub.R should be more than 100 times the leakage current I.sub.leak. Under this condition, the transistor Q.sub.1 can be activated.
Assuming that the standby current I.sub.SB is less than 1 .mu.A and the SRAM is of 4 mega-bit grade, a current of 250 fA per unit cell can be obtained.
Since the current I.sub.R, should be more than 100 times the leakage current I.sub.leak, the leakage current I.sub.leak can be ignored. Accordingly, the following equation (2) can be established. EQU I.sub.SB =I.sub.R =250fA/cell (2)
In the equation (2), the resistance of the resistor R.sub.1 should be 20 T.OMEGA., in order to obtain the current I.sub.R of 250 fA/cell. For obtaining the resistance of 20 T.OMEGA., the resistor R.sub.1 should have a thickness of 500 .ANG., a width of 0.6 .mu.m, and a length of 60 .mu.m. As a result, it is difficult to achieve a high integration.
For solving the problem that the high resistance-loaded SRAM is difficult to have an improved integration degree, CMOS type SRAMs have been developed. An example of such CMOS type SRAMs is illustrated in FIG. 2.
In the CMOS type SRAM, PMOS transistors Q.sub.5 and Q.sub.6 are used as load elements, in place of load resistors R.sub.1 and R.sub.2, as shown in FIG. 2. The CMOS type SRAM operates in the same manner as described in conjunction with FIG. 1.
Accordingly, the standby current I.sub.SB corresponds to the sum of the OFF current I.sub.off of the PMOS transistor Q.sub.6 and the leakage current I.sub.leak of the NMOS transistor Q.sub.1, as expressed by the following equation (3). EQU I.sub.SB =I.sub.off +I.sub.leak ( 3)
In this case, the leakage current I.sub.leak of the NMOS transistor Q.sub.1 should be considerably less than the ON current I.sub.on of the PMOS transistor Q.sub.5. For example, the ON current I.sub.on should be more than 100 times the leakage current I.sub.leak (I.sub.on &gt;I.sub.leak .times.100). Generally, the leakage current I.sub.leak of the NMOS transistor Q.sub.1 is about 10 fA.
Accordingly, assuming that the standby current I.sub.SB is less than 1 .mu.A and the SRAM is of 4 mega-bit grade, a current of 250 fA per unit cell can be obtained.
Consequently, the leakage current I.sub.leak in the equation (3) corresponds to 10 fA/cell (I.sub.leak =10 fA/cell) whereas the OFF current I.sub.off is not more than 250 fA/cell (I.sub.off .ltoreq.250 fA/cell).
Since the leakage current I.sub.leak is approximately equal to 10 fA/cell (I.sub.leak .apprxeq.10 fA/cell), the ON current I.sub.on of the PMOS transistor Q.sub.5 should be more than 100 times the leakage current I.sub.leak (I.sub.on &gt;I.sub.leak .times.100=1PA). Accordingly, a good current margin for retaining data is obtained. Assuming that a general data value is 10 nA, the current margin for retaining data corresponds to the ON/OFF current ratio of 10.sup.3 because the ON/OFF current ratio of the PMOS transistor is 10.sup.5 while the ON/OFF current ratio of the load resistor is 10.sup.2.
By virtue of such a characteristic, active researches for improving ON/OFF current ratios in PMOS thin film transistors used in CMOS type SRAMs have recently been made.
Now, a conventional PMOS thin film transister for improving the ON/OFF current ratio will be described in conjunction with the drawings.
FIGS. 3a to 3d are sectional views respectively illustrating a method for fabricating a conventional off-set type thin film transistor. In accordance with the method, an oxide film 2 and a body polysilicon layer 3 are sequentially deposited over a substrate 1, as shown in FIG. 3a. In the body polysilicon layer 3, ions for controlling a threshold voltage are implanted.
Over the entire exposed surface of the resulting structure, a gate oxide film 4, a polysilicon layer 5 for a gate and a first photoresist film 6 are deposited in this order, as shown in FIG. 3b.
Thereafter, a gate electrode region is defined by use of a light exposure process and a development process using a mask for a gate electrode pattern, as shown in FIG. 3c. The polysilicon layer 5 for the gate and the gate oxide film 4 are then selectively removed to form a gate electrode 5a. Subsequently, the first photoresist film 6 is removed.
As shown in FIG. 3d, a second photoresist film 9 is deposited to define a off-set region between the gate electrode 5a and a drain region. Using the gate electrode 5a and the second photoresist film 9 as a mask, p type impurity ions are implanted in a high concentration in the body polysilicon layer 3 to form a source region 10a and a drain region 10b.
FIGS. 4a to 4e are sectional views respectively illustrating a method for fabricating a conventional lightly doped off-set (LDO) type thin film transistor. In FIGS. 4a to 4e, elements corresponding to those in FIGS. 3a to 3d are denoted by the same reference numerals.
In accordance with this method, an oxide film 2 and a body polysilicon layer 3 are sequentially deposited over a substrate 1, as shown in FIG. 4a.
In place of the body polysilicon layer 3; an amorphous silicon layer may be formed. In this case, silicon ions are implanted in the amorphous silicon layer which is, in turn, subjected to an annealing at a temperature of 600.degree..+-.50.degree. C. for a long time. By these treatments, the amorphous silicon layer is formed into a polysilicon layer.
Thereafter, ions for controlling a threshold voltage are implanted in the body polysilicon layer 3.
Over the body polysilicon layer 3, a gate oxide film 4, a polysilicon layer 5 for a gate and a first photoresist film 6 are then deposited in this order, as shown in FIG. 4b.
Using a mask for a gate electrode pattern, the first photoresist film 6 is subjected to a light exposure process and a development process, thereby forming a first photoresist film mask 6a, as shown in FIG. 4c. Using the first photoresist film mask 6a as a mask, the polysilicon layer 5 for the gate and the gate oxide film 4 are then selectively removed to form a gate electrode 5a.
Subsequently, the first photoresist film mask 6a is removed. As shown in FIG. 4d, a second photoresist film 7 is deposited over the entire exposed surface of the resulting structure and then subjected to a light exposure process and a development process to expose a drain region disposed on one side of the gate electrode 5a. Using the second photoresist film 7 as a mask, p type impurity ions are implanted in a low concentration in the body polysilicon layer 3 to form a low concentration impurity region 8.
As shown in FIG. 4e, the second photoresist film 7 is then removed. Thereafter, a third photoresist film 9 is deposited over the entire exposed surface of the resulting structure. The third photoresist film 9 is then subjected to a light exposure process and a development process so that a source region disposed on the other side of the gate electrode 5a is exposed while the drain region disposed on one side of the gate electrode 5a is offset. Using the third photoresist film 9 as a mask, p type impurity ions are implanted in a high concentration in the exposed portion of the body polysilicon layer 3, thereby forming high concentration impurity regions 10a and 10b.
Operations of the conventional thin film transistors fabricated in the above-mentioned manners are the same as those of general PMOS transistors.
In other words, when a drive signal is applied to the gate electrode 5a, a channel is formed between the source region and the drain region. Accordingly, the source region and the drain region are communicated with each other.
However, the above-mentioned conventional thin film transistors have the following problems.
Although the off-set type thin film transistor fabricated in accordance with the method of FIGS. 3a to 3d can control the OFF current to be maintained at a lower level because the gate and the drain are offset, it can achieve an increased ON/OFF current ratio in that the ON current is also controlled to be at a lower level. On the other hand, the LDO type thin film transistor can control the ON current to be increased to a some high level because the low concentration impurity layer is formed in the off-set region. In this case, however, the OFF current is also controlled to be at a high level. As a result, the LDO type thin film transistor has a limitation on increasing the ON/OFF current ratio, even though its ON/OFF current ratio is higher than that of the off-set type thin film transistor.
A decrease in OFF current may be obtained by reducing the thickness of the body polysilicon layer in which the channel region is defined. However, such a reduced thickness of the body polysilicon layer results in an increase in surface resistance in the source and drain regions. As a result, a consumption of electric power is considerably increased. Consequently, there is a limitation on increasing the ON/OFF current ratio because the thickness of the body polysilicon layer can not be optionally reduced.